SOC Verification Using SystemVerilog
A thorough course that teaches System on Chip design verification fundamentals as well as coding in SystemVerilog. Learn in detail about the key ideas necessary for design verification flow.
What you'll learn
- Learn about the key ideas in the SOC/ASIC/VLSI design verification flow.
- Learn how to use System Verilog for Functional Verification.
- Prepare for and be qualified for a Verification position in the semiconductor sector.
- Udemy Certification is awarded upon successful completion of a course.
- You must be able to code, simulate, and verify SystemVerilog Testbenches.
Covers SOC/ASIC/VLSI design verification concepts and SystemVerilog language fundamentals, including connecting testbenches to designs, object-oriented programming, randomization, threads, and inter-process communication. Learners complete a project assignment building a testbench for an Ethernet switch and receive an introduction to verification methodologies. Afterwards they can code, simulate, and verify SystemVerilog testbenches for entry-level verification roles.
Who this course is for
Aspiring verification engineers or hardware developers preparing for semiconductor verification positions.